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LS2051 (also refer to LS4051) is high performance eight bit microcomputer designed and manufactured by our company and is compatible with MCS-51 instruction set, and its internal function, pin function, pin configuration, and electrical characteristics of pins are compatible with AT89C2051. LS2051 supports simultaneous operation of two independent or associated programs. The performance when only one program is executed is 1.27 times of that of AT89C2051, and the processing capacity is 2.55 times of AT89C2051 when two programs are executed simultaneously.
Features
Compatible with MCS-51 instruction setpins are compatible with AT89C2051. 2/4KB internal flash program memory, Endurance: 2000 times erase/write cycles. 3.0V to 5.5V operating range. 0Hz to 24 MHz frequencies. Two-level of Encryption of Program Memory. 128x8B internal SRAM. 15 programmable I/O ports20mA sink currentdrives LED directly. Six interrupt sources. Two 16-bit timer and counter. One programmable UART. SPI programming interface. One high-resolution on-chip Analog Comparator. Low power idle and power-down modes.
Description
LS2051 contains 2K bytes of program memory (LS4051 contains 4K bytes), 128 byte of data memory (SRAM), two 16-bit timer/counter, one five-vector secondary interrupt architecture , a single-kernel for execute two programs, fifteen IO ports, a full duplex serial port, a high-accuracy on-chip analogy comparator, oscillator and clock circuitry. The operating range of LS2051 is 0Hz to 24MHz, and supports the idle power saving mode and the power-down power saving mode which are software selectable. The idle mode stops the CPU, while allowing the SRAM, timer/counter, serial port and interrupt machine and the power-down system to continue functioning. The power-down mode saves the SRAM contents but freezes oscillator and turns all the internal clocks off. LS2051 achieves the function of double kernels, that is, it can execute one programming singly, and it can also execute associated or non-associated two programs concurrently. The performance of executing one program is 1.27 times of compatible chips, and that of
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processing two programs can reach 2.55 times of compatible chips at most.
Pin Description
Pin configuration and its multiplexing function of LS2051 are as Figure 1.
Figure 1: VCCSupply voltage GNDGround
LS2051 Pin Configuration
P1 port: an eight-bit programmable bi-directional I/O port. Pin P1.2 to P1.7 provide internal pull-ups. P1.0 and P1.1 serve as the positive input (AIN0) and the negative input (AIN1) of the on-chip comparator and with no internal pull-up, one can add pull-ups for the pins if needed. P1 port output buffer can absorb 20mA current and can drive LED directly. A pin of P1 can be used as input only after "1" is written into the pin; A pin can output "1" or "0" when "1" or "0" is written into the pin. P1 port is used as inputting port when chip is reset . When pins P1.2 to P1.7 are taken as inputting and are pulled down, they will produce original current because of their inside pull-up resistance (IIL). When programming, P1.5, P1.6 and P1.7 should correspond to programming interface signal, SPI-MOSI, SPI-MISO and SPI-CLK. Note that 4.7K ohm pull-up resistance should be added when the speed of I/O port is over 40 KHz. P3 port: P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups, P3.6 is the output of the on-chip comparator and is not connected outside the LS2051. Port 3's output buffer can sink 20mA and can drive LED directly. A pin of P3 can be used as input only after "1" is written into the pin; A pin can output "1" or "0" when "1" or "0" is written into the pin. P3 port is used as inputting port when chip is reset. When used as inputs, Port 3 pins are externally being pulled down and will produce current (IIL).
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Multiplexing function of P3 port is shown in Table 1. Note that 4.7K ohm pull-up resistance should be added when the speed of I/O port is over 40 KHz.
Port pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 Alternate Functions RXDserial input port TXDserial output port
INT0 external interrupt 0 INT external interrupt 1 1
T0 timer 0 input T1 timer 1 input
Table 1: Special Functions of Port P3 RST: Reset input. High is active, after power-on or power-down mode of chips, chips can execute smoothly only when the reset signal of 1s must be kept over 100us. Under other circumstance, holding the RST pin high for two machines cycle can reset the chip. Each machine cycle takes 12 oscillator or clock cycles. XTAL1: Input to the inverting amplifier of the internal oscillator and input to the internal clock generating circuit. XTAL2: Output from the inverting amplifier of the internal oscillator.
Clock Characteristics
Either quartz crystal or ceramic resonator may be used, as figure 2. XTAL1 is the input of external clock. When external clock is used, XTAL2 is left unconnected, as Figure 3. There is a divider inside LS2051 to perform the function of dividing-by-two and forming for output clock of internal oscillator or for external input clock from pins. Therefore there is no special requirement for external input clock, but it is must be in accordance with current and alternating standards of clock signal.
Fig 2: Clock Circuitry Using Internal Oscillator
Fig 3: Connection of External Clock
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When quartz crystal is adopted C1,C2=30pF10pF. When ceramic resonator is adopted C1,C2=40pF10pF.
Special Function Registers
The memory map for special function register (SFR) is shown in Table 2. The blank bytes are not defined in this version. They will return indeterminate values when being read.
B 6
Addr 0F8H 0F0H 0E8 H 0E0 H 0D8 H 0D0 H 0C8 H 0C0 H 0B8 H 0B0 H 0A8 H 0A0 H 98H
B0
B1
B2
B3
B4
B5
B7
Addr 0FFH
B 00000000
0F7H 0EF H
ACC 00000000
0E7H 0DF H
PSW 00000000
0D7 H 0CF H 0C7 H
IP XXX0000 0 P3 11111111 IE 0XX0000 0
0BF H 0B7 H 0AF H 0A7 H SBUF XXXXXXX X 9FH
SCON 00000000
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90H
P1 11111111 TCON 00000000 TMOD 00000000 SP 00000111 TL0 00000000 0 DPL 00000000 TL1 0000000 0 DPH 0000000 0 TH0 0000000 0 TH1 0000000 0 PCON 0XXX000 0
97H
88H
8FH
80H
87H
Table 2:
SFR Map and Reset Values
Note: IE `s d7 bit of Special Register is the interrupt enable bit for the main or first program, and d6 bit is the interrupt enable bit for the second program.
Restriction on Some Instructions
The instruction system of LS2051 is compatible with MCS-51, but one should pay attention to the following two restrictions when using LS2051 to develop application programs.
1MOVX Related Instructions, Data Memory
The internal data memory of LS2051 is 128 bytes, the depth of stack is 128bytes, accessing to the external data memory is not supported in LS2051, nor is the external program memory. Therefore, no MOVX related instructions should be included in application programs. A typical 51 assembler will still assemble such instructions even if they read and/or write external memories. Users should know the physical features and limitations of LS2051 and adjust instructions correspondingly.
2Branching Instructions
The unconditional branching instructions , such as LCALL, LJMP, ACALL, AJMP, SJMP and JMP @A+DPTR, are executed correctly only when the destination branching addresses fall within 000H to 7FF, otherwise programs might go wrong. The restrictions of conditional branching instructions, such as CJNE, DJNZ, JB, JNB, JC, JNC, JBC, JZ and JNZ, are the same as that of unconditional branching instructions.
Other Restrictions
The reset time should be over 100us when chips are power-on and/or waked from power-down mode. It won't response to an interrupt when the interrupt service for the interrupt is suspended. If idle mode is entered during an interrupt is being served, the idle mode can not be waked up by the interrupt.
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Both programs have their own ACC DPTR B PSW and SP, but the main program (the first program) has 32 general registers while the second has 8. It should be pay more attention to the stack operations in the development of the second program. The design of the main program is completely the same as that of AT89C2051. If the second program is not used, an LS2051 is totally compatible with AT89C2051. The interrupt processing of LS2051 is more active and effective than that of AT89C2051 because of the peculiar second program processing engine of LS2051. If the interrupt for the main program is enabled while the interrupt for the second program is not enabled, the main program will deal with all the interrupts. If the interrupts for both programs are enabled and the second program has not been started to execute or not been designed, both programs may deal with interrupts, this is automatically arranged by the chip itself. Once the second program is started to execute, it won't be interrupted. When an interrupt comes, LS2051 jumps into the interrupt service routine before the current instruction is done, while 89C2051 is after the current instruction is done. Pay more attention to the possible confliction for public resources when two programs are employed. The baud rate of LS2051's Serial way 0 is Fosc/24, and the baud rate of serial way 2 is Fosc/64 and Fosc/128, while that in 89C2051 are Fosc/12, Fosc/32 and Fosc/64. If P1 port and P3 port are used to input/output in a rate over 40 KHz, the ports should be pulled up with external resistances of 4.7K.
Program Memory Lock Bit
On the chip are two lock bits which can be left un-programmed (U) or can be programmed (P) to obtain program lock, as shown in Figure 3, lock bit can be turned to invalidation only by erasing .
LB1 U P P LB2 U U P Function No program lock Further the programming of Flash is disabled Further the programming of Flash is disabled, also verify is disabled.
Figure 3:
Program Lock of LS2051
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Work mode
1Idle mode
Idle state can be entered through program instructions, and can be terminated by any enable interrupt or a hardware reset. While in idle state, CPU stops to work, but allowing SRAM, timer/counter, serial ports and interrupt system to continue to function. P1.0 and P1.1 should be set to "0" if no external pull-ups are used, or set to "1" if external pull-ups are used to decrease further power consumption. It should be noted that when idle state is terminated by a hardware reset, the chip normally resumes to work after two machine cycles of the reset. During this time, internal SRAM is inhibited to access, but the port pins are not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes to enter an idle state should not be to write to a port pin.
2. Power-down mode
A power-down state can be entered through program instructions, and can be terminated by hardware reset. In the power down state, the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip SRAM and Special Function Registers retain their values during the power down state. Reset redefines the SFRs but does not change the on-chip SRAM. The reset signal is invalid until VCC is restored to its normal operating level, and the reset signal must be held active long enough to allow the oscillator to restart and stabilize. P1.0 and P1.1 should be set to "0" if no external pull-ups are used, or set to "1" if external pull-ups are used, this can help to decrease power consumption.
Programming the Flash
LS2051 uses SPI protocol to programming the flash. And special programming driver and cables are also provided. LS2051's SPI interfaces will not provide read operation to the internal flash in order to strengthen the security of user's application software.
SPI Programming Agreement
SPI interface of LS2051 includes RST, SCK(P1.7), MOSI(P1.5) and MISO(P1.6) signals , as Figure 5. Chips are in programmable state when reset input RST is "1". At this time it can send programming instructions and codes through SCK and MOSI, MOSI is programming fault indication. Chips are in normal operating state when the reset signal is "0".
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Figure 5:
Flash Programming Interface Signals
SPI adopts synchronous serial way to sending byte data, its timing sequence is as Figure 6.
Figure 6:
SPI Interface Sequence
When a LS2051 is in programming state, serial data carried by MOSI are sampled at the up edge of SCK, the successive eight bits are set to be one byte, and the seventh bit of a byte is transmitted first. MISO is the verifying output. LS2051 will verify each byte of data. When a byte is failed to pass the verification, MISO will output "1" until next correct verification, and MISO will output "0".
Programming order Write Flash: the sequence of order code is AA-50-AX-AY-data. When SPI interface receives these five bytes successively, chips enter Flash writing operation. The first byte AA and the second byte 50 are order codes, the third byte is high 6-bit address of Flash, the fourth byte is low 6-bit address of Flash, and the fifth byte is data to be input. Erase FlashOrder code sequence AA-8A or AA-E4. LS2051allows to erase whole 2KB Flash space. When SPI receives these two bytes successively, chips enter sequence of Flash erasing operation: the first byte is AA, and the second byte is 8A or E4. LS2051's SPI does not support read operation to Flash in order to strength lock performance.
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Erasing Sequence of Flash
When SPI receives the order code AA and 8A, chips enter the flash erasing sequence, the sequence is shown in Figure 7. The order code AA and 8A must be transmitted successively , any other information should not be inserted. Other order codes should not sent to SPI interface during the erasing period, otherwise it will cause failure of erasing operation.
Erasing order Figure 7: Writing sequence of Flash Erasing Sequence of Flash
Erasing
When SPI receives AA-50-AX-AY-data bytes, chips enter the flash writing sequence. Order codes should be transmitted successively, any other information should not be inserted. The flash writing sequence is shown in Figure 8. During the writing period, the other order codes should not be transmitted to SPI interface, or it will cause failure of writing operation. There will be auto-verification after finishing writing a byte. If it is correct, MOSI will output 0, if not, MOSI will output 1. The failure of some byte's writing will not affect the writing operation of following bytes, but rewriting of the byte will not succeed.
Write order Figure 8:
write address Flash Sequence
write data
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Limit Parameter
The LS2051's limit parameters is as Table 4.
Operating temperature Storage temperature -40 to -60 to +85 +125
Voltage on Pin with Respect to Ground
VCC ICC
-1.0V to +7.0V 6.6V 25.0mA
Table 4: LS2051 Limit Parameters
Current characteristic
LS2051's direct current characteristic is as Table 5.
Sym VIL VIH VIH1 VOL VOH IIL ITL ILI VOS VCM RRST CIO ICC
Parameter Input Low-voltage Input High-voltage Input High-voltage Output Low-voltage Output High-voltage Logical 0 Input Current Logical 1 to 0 Transition Current Input Leakage Current Comparator Input Offset Voltage Comparator Input Common Mode Voltage Reset Pull-down Resistor Pin Capacitance Power Supply Current
Condition
Min -0.5
Max 0.2 Vcc - 0.1 Vcc + 0.5 Vcc + 0.5 0.5
Units V V V V V
(Except XTAL1, RST) (XTAL1, RST) Iol = 20 mA, Vcc = 5V
0.2 Vcc + 0.9 0.7 Vcc
Ioh = -80 A, Vcc = 5V*10% Vin = 0.45V Vin = 2V, Vcc = 5V*10%
2.4 -50 -750 10 20 0 30 Vcc 70 10 20
A A A mV V K pF mA
0 < Vin < Vcc Vcc= 5V
Test Freq. = 1 MHz, TA = 25C Active Mode, 12 MHz, Vcc=5V
Table 5:
Current Parameters of LS2051
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Notes
Under the stable circumstance (not instant), IOL is restricted the following
The max allowable value of each port IOL is 20mA. The max sum of all the output port IOL is 80mA. If IOL exceeds test condition allowable value, and then VOL may exceed allowable value by relatively, but it can guarantee port value will exceed value gained from test condition as in Table 5.
Instruction set
Mnemonics definition table
In order to convenience the description to LS2051, the mnemonics are as table 6.
Mnemonics Rn Direct @Ri #data #data16 Addr16 Addr11 Rel bit Description Register R7R0 of the currently selected Register Bank. 8-bit internal data location's address. This could be an Internal Data RAM location (0127) or a SFR [i.e., I/O port, control register, status register, etc. (128255)]. 8-bit internal data RAM location (0255) addressed indirectly through register R1 or R0. 8-bit constant included in instruction. 16-bit constant included in instruction. 16-bit destination address. Used by LCALL & LJMP. A branch can be anywhere within the 64K-byte Program Memory address space. 11-bit destination address. Used by ACALL & AJMP. The branch will be within the same 2K-byte page of program memory as the first byte of the following instruction Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is b128 to a127 bytes relative to first byte of the following instruction. Direct Addressed bit in Internal Data RAM or Special Function Register.
Table 6: Mnemonics Descriptions
Instructions
LS2051 instructions and their operations are show in Table 7.
Instruction Byte Oscillator Period Description
ARITHMETIC OPERATIONS 1 ADD A,Rn 2 ADD A,direct 3 ADD A,@Ri 4 ADD A,#data 1 2 1 2 12 12 12 12 Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator
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5 ADDC A,Rn 6 ADDC A,direct 7 ADDC A,@Ri 8 ADDC A,#data 9 SUBB A,Rn 10 SUBB A,direct 11 SUBB A,@Ri 12 SUBB A#data 13 INC A 14 INC Rn 15 INC direct 16 INC @Ri 17 INC DPTR 18 DEC A 19 DEC Rn 20 DEC direct 21 DEC @Ri 22 MUL AB 23 DIV AB 24 DA A LOGICAL OPERATIONS 25 ANL A,Rn 26 ANL A,direct 27 ANL A,@Ri 28 ANL A,#data 29 ANL direct,A 30 ANL direct,#data 31 ORL A,Rn 32 ORL A,direct 33 ORL A,@Ri 34 ORL A,#data 35 ORL direct,A 36 ORL direct,#data 37 XRL A,Rn 38 XRL A,direct 39 XRL A,@Ri 40 XRL A,#data 41 XRL direct,A
1 2 1 2 1 2 1 2 1 1 2 1 1 1 1 2 1 1 1 1
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
Add register to Accumulator with Carry Add direct byte to Accumulator with Carry Add indirect RAM to Accumulator with Carry Add immediate data to Acc with Carry Subtract Register from Acc with borrow Subtract direct byte from Acc with borrow Subtract indirect RAM from ACC with borrow Subtract immediate data from Acc with borrow Increment Accumulator Increment register Increment direct byte Increment direct RAM Increment Data Pointer Decrement Accumulator Decrement Register Decrement direct byte Decrement indirect RAM Multiply A & B Divide A by B Decimal Adjust Accumulator
1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
AND Register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte AND immediate data to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte OR immediate data to direct byte Exclusive-OR Register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte
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42 XRL direct,#data 43 CLR A 44 CPL A 45 RL A 46 RLC A 47 RR A 48 RRC A 49 SWAP A DATA TRANSFER 50 MOV A,Rn 51 MOV A,direct 52 MOV A,@Ri 53 MOV A,#data 54 MOV RnA 55 MOV Rn,direct 56 MOV Rn,gdata 57 MOV direct,A 58 MOV direct,Rn 59 MOV direct1, direct2 60 MOV direct,@Ri 61 MOV direct,#data 62 MOV @Ri,A 63 MOV @Ri,direct 64 MOV @Ri,#data 65 MOV DPTR, #data16 66 MOVC A, @A+DPTR 67 MOVC A, @A+PC 68 PUSH direct 69 POP direct 70 XCH A,Rn 71 XCH A,direct 72 XCH A,@Ri 73 XCHD A,@Ri
3 1 1 1 1 1 1 1
12 12 12 12 12 12 12 12
Exclusive-OR immediate data to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator Left Rotate Accumulator Left through the Carry Rotate Accumulator Right Rotate Accumulator Right through the Carry Swap nibbles within the Accumulator
1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 2 2 1 2 1 1
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 24 24 12 12 12 12 12 12
Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move Accumulator to register Move Accumulator to register Move Accumulator to direct byte Move register to direct byte Move direct2 byte to direct1 Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move direct byte to indirect RAM Load Data Pointer with a 16-bit constant Move Code byte relative to DPTR to Acc Move Code byte relative to PC to Acc Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order Digit indirect RAM with Acc
BOOLEAN VARIABLE MANIPULATION 74 CLR C 75 CLR bit 76 SETB C 1 2 1 12 12 12 Clear Carry Clear direct bit Set Carry
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77 SETB bit 78 CPL C 79 CPL bit 80 ANL C,bit 81 ANL C,/bit 82 ORL C,bit 83 ORL C,/bit 84 MOV C,bit 85 MOV bit,C 86 JC rel 87 JNC rel 88 JB bit,rel 89 JNB bit,rel 90 JBC bit,rel PROGRAM BRANCHING 91 ACALL addr11 92 LCALL addr16 93 RET 94 RETI 95 AJMP addr11 96 LJMP addr16 97 SJMP rel 98 JMP @A+DPTR 99 JZ rel 100 JNZ rel 101 CJNE A,direct,rel 102 CJNE A,#data,rel 103 CJNE Rn, #data, rel 104 CJNE @Ri, #data, rel 105 DJNZ Rn,rel 106 DJNZ direct,rel 107 NOP
2 1 2 2 2 2 2 2 2 2 2 3 3 3
12 12 12 12 12 12 12 12 12 12 12 12 12 12
Set direct bit Complement Carry Complement direct bit AND direct bit to CARRY AND complement of direct bit to Carry OR direct bit to CARRY OR complement of direct bit to Carry Move direct bit to Carry Move Carry to direct bit Jump if Carry is set Jump if Carry is not set Jump if direct Bit is set Jump if direct Bit is not set Jump if direct Bit is set & clear bit
2 3 1 1 2 3 2 1 2 2 3 3 3 3 2 3 1
12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12
Absolute Subroutine Call Long Subroutine Call Return from Subroutine Return from interrupt (Program 1). Stop running (Program 2) Absolute Jump (2K) Long Jump (64K) Short Jump (relative addr, -128+127bytes)
Jump indirect relative to the DPTR Jump if Accumulator is Zero Jump if Accumulator is not Zero Compare direct byte to Acc and Jump if Not Equal Compare immediate to Acc and Jump if Not Equal Compare immediate to register and Jump if Not Equal Compare immediate to indirect and Jump if Not Equal Decrement register and Jump if Not Zero Decrement direct byte and Jump if Not Zero No Operation
INSTRUCTIONS REALETED TO CONCURRENT PROGRAMS MOV 0FEH,#data MOV 0FCH,#addr8 3 3 12 12 Program 2 Stops Running Jump and Set the Synchronizing-bit to be One if the Synchronizing-bit is Zero
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MOV 0FBH,#addr8 MOV 0FFH,#addr8 MOV 0FDH, #1 MOV 0FDH, #0
3 3 3 3
12 12 12 12
Jump and Set the Synchronizing-bit to be Zero if the Synchronizing-bit is not Zero Load Program 2 to execute (Start Address is addr8) Set the Synchronizing-bit to be One Set the Synchronizing-bit to be Zero
Table 7:
LS2051Instruction Set
Examples for Two programs to Execute Concurrently
1. The sample program for running two programs concurrently: two programs execute their own algorithms to calculate something concurrently, and then the results will be added up to produce the final results. The final result will be then output through P1 port. The final results are 07H, 38H, 39H, 07H, 07H, 04H, 0BH. The program is as follows. MAIN: MOV 0FFH,#ROAD1 MOV A,#2 ADD A,#5 INC A SUBB A,#4 MOV R0,A MOV 0FBH,#$ Judge whether synchronous flag is 1, if it is 1, then continue Major program executes in the first path Turn program in the first path on A=2 A=7 A=8 A=4
; to execute; if it is 0, then execute this statement always. MOV A,12H MOV P1,A MOV A,R0 MOV P1,A ADD A,12H MOV P1,A AJMP $ Output from P1 port, A=4 A=0BH Output from P1 port Program in the first path cycles here A=7
ROAD1: MOV A,#7
The entrance address of program in the second path A=7
MOV P1,A MOV B,#8
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Output from P1 port
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MUL AB MOV P1,A INC A MOV P1,A SUBB A,#50 MOV P1,A MOV 12H,A MOV 0FDH,#1 RETI ; # instant number.
B=0 A=56
A=57
A=7
Set synchronous flag to be 1 The second program ends. This can be replaced by MOV 0FEH
2.
Play two songs by two programs concurrently: the main program play the song
(named Sweet Olive Blooming in August) edited by C language, and the output port is P1.0. The second program play the song named Happy Birthday, assembled by assembler, and output through Port P1.1. The example includes the following programs: music_c_asm.c, road1.a51, loadp.a51. Sweet Olive Blooming in August: music_c_asm.c: extern void loadp(void) #include #include // crystal applied in this example is 11.0592MHZ unsigned char n=0; //n is beat constant variable
unsigned char temp_th1=0,temp_tl1=0; unsigned char code music_tab[] = { //format is frequency constant, beat constant, frequency constant, beat constant. 0x20, 0x40, 0x1C , 0x10, 0x1C, 0x10, 0x18 , 0x40,
0x18, 0x30, 0x1C , 0x10, 0x18, 0x10, 0x20 , 0x10,
0x1C, 0x20, 0x20 , 0x20, 0x1C, 0x20, 0x18 , 0x20, 0x20, 0x80, 0xFF , 0x20, 0x20, 0x15, 0x20 , 0x1C, 0x40, 0x20, 0x20 , 0x2B, 0x20, 0x30, 0x80 , 0xFF, 0x30, 0x1C, 0x10 , 0x18, 0x20, 0x20, 0x20 , 0x26, 0x20, 0x26, 0x20 , 0x20, 0x20, 0x20, 0x1C , 0x10,
0x18, 0x10, 0x20 , 0x20, 0x30, 0x20, 0x2B , 0x40, 0x18, 0x10, 0x20 , 0x20,
0x26, 0x20, 0x2B , 0x20, 0x20, 0x20, 0x1C , 0x10, 0x26, 0x20, 0x2B , 0x20,
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0x30, 0x20, 0x2B , 0x40, 0x18, 0x20, 0x15 , 0x20, 0x26, 0x40, 0x20 , 0x20, 0x20, 0x20, 0x30 , 0x80, 0x20, 0x10, 0x1C , 0x10, 0x2B, 0x20, 0x30 , 0x20, 0x1F, 0x05, 0x20 , 0x10, 0x26, 0x20, 0x2B , 0x20, 0x20, 0x30, 0x1C , 0x10,
0x20, 0x30, 0x1C , 0x10, 0x1C, 0x20, 0x20 , 0x20, 0x2B, 0x20, 0x26 , 0x20, 0x20, 0x30, 0x1C , 0x10, 0x20, 0x20, 0x26 , 0x20, 0x2B, 0x40, 0x20 , 0x15, 0x1C, 0x10, 0x20 , 0x20, 0x30, 0x20, 0x2B , 0x40, 0x18, 0x20, 0x15 , 0x20,
0x1C, 0x20, 0x20 , 0x20, 0x26, 0x40, 0x20 , 0x20, 0x2B, 0x20, 0x26 , 0x20, 0x20, 0x30, 0x1C , 0x10, 0x20, 0x20, 0x26 , 0x40, 0x15, 0x40, 0x13 , 0x40, }; void int0() interrupt 1 // apply interrupt 0 to controlling beat { TH0=0xd8; TL0=0xef; n--; } void int1() interrupt 3 // apply interrupt 1 to controlling music in the second path { TL1=temp_tl1; TH1=temp_th1; P1_1=~P1_1; } void delay (unsigned char m) // control frequency delay { unsigned i=3*m; while(--i); } 0x20, 0x20, 0x30 , 0x30, 0x18, 0x40, 0x1C , 0x20, 0x13, 0x60, 0x18 , 0x20, 0x18, 0x80, 0x00
void delayms(unsigned char a) // millisecond delay sub-programs { while(--a); }
17 Update Date 5/27/2008-1-16 HuNan Hochip Times Microelectronics Co.,Ltd
//adopt (--a) rather than while(a--);
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void main() { unsigned char p,m; unsigned char i=0; TMOD&=0xff; TMOD|=0x11; TH0=0xd8; TL0=0xef; IE=0x8a; loadp(); play: while(1) { a: p=music_tab[i]; if(p==0x00) { i=0; delayms(1000); goto play; } // if there is end signal, delay 1 second, do it again from the beginning. //load the second program //m is frequency constant variable
else if(p==0xff) { i=i+1; delayms(100); TR0=0; goto a; } // If there is rest, delay100ms, and then continue to select the next note. else
{ m=music_tab[i++]; n=music_tab[i++]; } // Select frequency constants and beat constants
TR0=1; //turn on timer 0 while(n!=0) {
18 Update Date 5/27/2008-1-16 HuNan Hochip Times Microelectronics Co.,Ltd
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P1_0=~P1_0; delay(m); } // wait for completion of beat and output audio frequency from P1 port.
TR0=0; // turn off timer 0 } }
Loader program of the second program loadp.a51 extrn code(road1) NAME LOADP
LOADP1 SEGMENT CODE PUBLIC RSEG loadp: USING MOV RET END Happy Birthday road1.a51 extrn data(temp_th1) extrn data(temp_tl1) 0 0FFH,#ROAD1 ;start the second path and execute ROAD1 on it. loadp LOADP1
NAME ROAD11
ROAD1 SEGMENT CODE
PUBLIC ROAD1 RSEG ROAD1: ROAD11
USING start0:
0
mov 60h,#00h next: mov a,60h mov dptr,#table movc a,@a+dptr mov r2,a temporarily jz end1
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;select indicator of sight-sing code ; load A to sight-sing code ;till table select sight-sing code
; store selected sight-sing codes to R2
;Whether select 00( end code)?
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anl a,#0fh mov r5,a mov a,r2 swap a anl a,#0fh jnz sing clr tr1 jmp d1 sing: dec a mov 63h,a rl a mov dptr,#table1 ;value movc a,@a+dptr mov th1,a mov temp_th1,a mov a,63h rl a inc a movc a,@a+dptr ; value mov tl1,a mov temp_tl1,a setb tr1 d1: call delay inc 60h
; if not, select low 4 bit( note code) ; store beat code to R5 ; A load A to sight-sing code again ; interchange of high and low four bits ; select low four bits( notes) ; whether the selected note is zero? ; If so, it is aphonic
; selected note minus 1( not include 0) ;store (22H). ;multiply 2 ;till table1 select comparable high byte count
; store selected byte to TH1 ;store selected byte to (21H) ;reload selected note ;multiply 2 ;plus 1 ;till table1 select comparable low byte count
;store the selected high-bit type to TL1 ;store the selected high-bit byte to (20H) ;start timer 0 ; basic unit time 1/4 beat 187millisecond ;select sight-singing indicator plus one
jmp next end1: clr tr1 jmp start0 delay: mov r7,#02h d2: mov r4,#187 d3: mov r3,#248 djnz r3,$ djnz r4,d3 djnz r7,d2 djnz r5,delay
20 Update Date 5/27/2008-1-16
; select a code ; terminate timer1 ;loop? ;187 millisecond
;decide beat
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ret table1: dw 64260,64400,64524,64580 dw 64684,64777,64820,64898 dw 64968,65030,65058,65110 dw 65157,65178,65217 table: ;1 db 82h,01h,81h,94h,84h,0b4h,0a4h,04h,82h,01h,81h,94h,84h,0c4h,0b4h,04h ;2 db 82h,01h,81h,0f4h,0d4h,0b4h,0a4h,94h,0e2h,01h,0e1h,0d4h,0b4h,0c4h,0b4h,04h ;3 db 82h,01h,81h,94h,84h,0b4h,0a4h,04h,82h,01h,81h,94h,84h,0c4h,0b4h,04h ;4 db 82h,01h,81h,0f4h,0d4h,0b4h,0a4h,94h,0e2h,01h,0e1h,0d4h,0b4h,0c4h,0b4h,04h,00h RET END
21 Update Date 5/27/2008-1-16 HuNan Hochip Times Microelectronics Co.,Ltd
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Product order
Frequency 0 to 24MHz 0 to 24MHz voltage 3.0V to 5.5V 3.0V to 5.5V Product Order LS2051-224SJI LS4051-224SJI LS2051-224PJI LS4051-224PJI packaging 20S 20P3 Operating range -40to 85 -40to 85
Packaging information
LS2051/LS4051 adopts 20 leads and 0.300" wide SOIC packing, as in Figure 9, the dimensions are in inches and millimeters.
Figure 9
LS2051/LS4051 packagingin SOIC
22 Update Date 5/27/2008-1-16 HuNan Hochip Times Microelectronics Co.,Ltd
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LS2051/LS4051 adopts 20 leads and 0.300" wide PDIP packing, as in Figure 10, the dimensions are in inches and millimeters.
Figure 10 LS2051/LS4051 packagingin PDIP
23 Update Date 5/27/2008-1-16 HuNan Hochip Times Microelectronics Co.,Ltd

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